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By M. Gasteier, S. Liao, X. Song on the crossing distribution problem, J.-Y. Jou on two-level logic minimization for low power, F. Vahid on procedure cloning, Q. Wang, G. Yeap on power reduction and power delay trade-offs, others M. Glesner

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In Proceedings of the IEEE International Symposium on Circuits and Systems. 2160–2163. , AND ASHAR, P. 1998. Guarded evaluation: Pushing power management to logic synthesis/design. IEEE Trans. -Aided Des. ), 1051–1060. YE, W. AND IRWIN, M. J. 1999. Power analysis of gated pipeline registers. In Proceedings of the Twelfth Annual IEEE International ASIC/SOC Conference. 281–285. Received January 2003; revised August 2003; accepted March 2004 ACM Transactions on Design Automation of Electronic Systems, Vol.

The number of such paths extracted from an input DFG is kept small, just enough to have considered all operations within the DFG. In fact, we can find such a set of paths for a DFG in polynomial time. Our technique to perform the actual assignment of operations to control steps is based on weighted noncrossing bipartite matching. This approach is fundamentally different from list scheduling and force-directed scheduling, and path-based scheduling in nature. Moreover, at the local level, we can provide theoretical guarantees on the quality of the operation-control step assignment for individual operation chains.

2002] have been incorporated into scheduling algorithms in the past. In this work we will introduce two other objective functions and show how the cost function of our algorithm can be easily adjusted to include either of those. We will discuss these objective functions in Section 3. The objective function is maximized under a set of constraints. For our scheduling problem the following constraints are given: — For each operation a start time must be defined. — Data dependencies imposed by the DFG must be obeyed.

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ACM Transactions on Design Automation of Electronic Systems (January) by M. Gasteier, S. Liao, X. Song on the crossing distribution problem, J.-Y. Jou on two-level logic minimization for low power, F. Vahid on procedure cloning, Q. Wang, G. Yeap on power reduction and power delay trade-offs, others M. Glesner


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