Analog circuit design : high-speed clock and data recovery, - download pdf or read online

By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

ISBN-10: 1402089430

ISBN-13: 9781402089435

ISBN-10: 1402089449

ISBN-13: 9781402089442

Analog Circuit Design includes the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit layout. every one half discusses a selected to-date subject on new and useful layout rules within the region of analog circuit layout. every one half is gifted via six specialists in that box and state-of-the-art info is shared and overviewed. This publication is quantity 17 during this winning sequence of Analog Circuit Design.

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Extra resources for Analog circuit design : high-speed clock and data recovery, high-performance amplifiers, power management

Example text

5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking,” Proceedings of the ISSCC, IEEE, February 2001, pp. 64–65. 7. S. A. Horowitz, “A semidigital dual delay-locked loop,” IEEE JSSC, Vol. 32, No. 11, November 1997, pp. 1683–1692. Mixed-Signal Implementation Strategies for High Performance Clock and Data Recovery Circuits Michael H. Perrott Abstract In implementing high performance clock and data recovery (CDR) circuits, there is an interesting tradeoff offered between analog and digital circuit implementations.

2745–2757. 4. T. 13 ␮m CMOS”, of the 30th European Solid-State Circuits Conference, September 2004, pp. 487–490. 5. G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased techniques”, IEEE JSSC, Vol. 31, No. 11, November 1996, pp. 1723–1732. 6. H. , “5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking,” Proceedings of the ISSCC, IEEE, February 2001, pp. 64–65. 7. S. A. Horowitz, “A semidigital dual delay-locked loop,” IEEE JSSC, Vol. 32, No. 11, November 1997, pp.

5 Gb/s in FC; Cable and backplane equalization is a common requirement, even if at different frequencies and channel losses; The maximum frequency difference between a FC transmitter and receiver is limited to +/– 200 ppm, while in SATA and SAS, for EMI suppression, the transmitted data can be modulated in frequency by a 30 kHz triangular shape, with a maximum amplitude of 5000 ppm (Spread Spectrum Clock – SSC); FC must assure shorter locking time (2500 bits) and serial to parallel data latency.

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Analog circuit design : high-speed clock and data recovery, high-performance amplifiers, power management by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier


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